In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout(s) can include metal interconnect layers or metal connectivity layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout processes, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks. Such routing between circuit blocks is typically done using one or more metal connectivity layers for each signal path. In most modern ASIC designs, at least five layers of metal connectivity are employed.
Referring now to FIG. 1A, a logical diagram of a typical signal path is shown. A signal path generally has a plurality of circuit blocks (e.g., circuit blocks 101-105) with “nets” or wires 111-114 communicatively coupled between circuit blocks. A signal path generally has flip-flops or other state memory devices at each end of the path (e.g., circuit blocks 101 and 105), with logic gates or other logical operation circuit blocks between the flip-flops (e.g., circuit blocks 102-104). Typically, a signal path is designed and/or required to propagate a signal from a beginning flip-flop 101 to an ending flip-flop 105 during one clock pulse. Therefore, when the circuit blocks and nets of a signal path are placed and routed on an integrated circuit device, the propagation delay of the wires that form the nets must be taken into account.
In conventional place-and-route flows, circuit blocks or “cells” are first placed in desired locations and sized (e.g., had their drive strength adjusted by changing transistor sizes and/or adding buffer stages) in accordance with a projected routing and capacitive load based on these desired cell locations. Then, signals are actually routed between the circuit blocks. A standard cell is a specific design for each gate in the library. With advancements in integrated circuit fabrication processes, the routing area is becoming relatively more important than the total number of transistors used with respect to the overall area of ASIC designs. Since the majority of ASIC routing is performed automatically, standard cell sizes are generally used to support place-and-route tools. Thus, referring now to FIG. 1B, circuit blocks 101-105 may be placed into cells of integrated circuit layout 120, where the height of each cell in rows R1 through R6 is the same. Although nets 111-114 are shown as straight logical interconnections between circuit blocks 101-105, wires are typically placed on horizontal and vertical wire tracks in the layout.
After wires are placed, the timing of the signal path is generally evaluated. Typically, capacitances of the actual resultant signal paths are extracted and provided to a simulator and/or timing closure tool. If the circuit meets the timing specifications for the design, timing closure has been obtained. However, if the circuit fails timing closure, adjustments to the circuit block placement and/or routing must be done. This process must be repeated until timing closure is met, delaying the completion of the overall design. In particular, overdriven signals or signals with relatively long paths resulting from such conventional solutions are susceptible to hold time violations. The signal paths must then be re-routed and/or the cells re-sized as part of one or more iterations in order to ultimately meet the timing constraints.
Given the increasing demands on circuit designers to more quickly create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure optimal cell sizing in an automated place-and-route flow. Increasing the complexity, flexibility, and/or functionality of the circuitry on a chip exacerbates these challenges.
In addition, re-validating timing for each change to a placement and routing solution can be very computationally intensive. Therefore, it is desirable to provide methods for predetermining outer boundaries for signal path characteristics (e.g., capacitance of the wires) where timing constraints can still be satisfied, so that nets can be re-routed to satisfy other conditions (e.g., to solve routing congestion problems) without violating timing constraints.
This “Background” section is provided for background information only. The statements in this “Background” are not an admission that the subject matter disclosed in this “Background” section constitutes prior art to the present disclosure, and no part of this “Background” section may be used as an admission that any part of this application, including this “Background” section, constitutes prior art to the present disclosure.